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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/01/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY mux21_1bit IS
	PORT (	in0,in1			: IN  STD_LOGIC;	-- Multiplexer inputs	
			sel				: IN  STD_LOGIC;	-- Multiplexer select
      		q_m	 			: OUT STD_LOGIC 	-- Multiplexer output
			);
END mux21_1bit;

ARCHITECTURE behav OF mux21_1bit IS
BEGIN
	PROCESS (in0,in1,sel)
	BEGIN
		IF sel = '0' THEN
			q_m <= in0;
		ELSIF sel = '1' THEN
			q_m <= in1;
		END IF;
	END PROCESS;
END behav;



